? semiconductor components industries, llc, 2016 february, 2016 ? rev. 1 1 publication order number: ncp720/d ncp720 350ma, very low dropout bias rail cmos voltage regulator the ncp720 is a 350 ma vldo equipped with nmos pass transistor and a separate bias supply voltage (v bias ). the device provides very stable, accurate output voltage with low noise suitable for space constrained, noise sensitive applications. in order to optimize performance for battery operated portable applications, the ncp720 features low i q consumption. the wdfn6 2 mm x 2 mm package is optimized for use in space constrained applications. features ? input voltage range: 0.8 v to 5.5 v ? bias voltage range: 2.4 v to 5.5 v ? fixed output voltage device ? output voltage range: 0.8 v to 2.1 v ? 2% accuracy over temperature ? ultra?low dropout: 110 mv typically at 350 ma ? very low bias input current of typ. 80 a ? very low bias input current in disable mode: typ. 0.5 a ? low noise, high psrr ? built?in soft?start with monotonic v out rise ? stable with a 2.2 f ceramic capacitor ? available in wdfn6 ? 2 mm x 2 mm package ? these are pb?free devices typical applications ? battery?powered equipment ? smartphones, tablets ? cameras, dvrs, stb and camcorders bias in en out gnd 2.2 f v out 1.5 v @ 350 ma v bias v in v en ncp720 figure 1. typical application schematics www. onsemi.com see detailed ordering, marking and shipping information on page 8 of this data sheet. ordering information marking diagram wdfn6 case 511br pin connections thermal t pad 1 2 3 6 5 4 out nc en in gnd bias (top view) xx = specific device code m = date code xx m 1
ncp720 www. onsemi.com 2 en current limit thermal limit uvlo + ? voltage reference in bias gnd out enable block figure 2. simplified schematic block diagram pin function description pin no. pin name description 1 out regulated output voltage pin 2 n/c not internally connected 3 en enable pin. driving this pin high enables the regulator. dr iving this pin low puts the regulator into shutdown mode. 4 bias bias voltage supply for internal control circuits. this pi n is monitored by internal under-voltage lockout circuit. 5 gnd ground pin 6 in input voltage supply pin pad should be soldered to the ground plane for increased thermal performance. absolute maximum ratings rating symbol value unit input voltage (note 1) v in ?0.3 to 6 v output voltage v out ?0.3 to (v in +0.3) 6 v chip enable and bias input v en, v bias ?0.3 to 6 v output short circuit duration t sc unlimited s maximum junction temperature t j 150 c storage temperature t stg ?55 to 150 c esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection (except out pin) and is tested by the following methods: esd human body model tested per eia/jesd22?a114 esd machine model tested per eia/jesd22?a115 latchup current maximum rating tested per jedec standard: jesd78. thermal characteristics rating symbol value unit thermal characteristics, wdfn6 2 mm x 2 mm thermal resistance, junction?to?air (note 3) r ja 65 c/w 3. this data was derived by thermal simulations based on the jedec jesd51 series standards methodology. only a single device mou nted at the center of a high k (2s2p) 3in x 3in multilayer board with 1?ounce internal planes and 2?ounce copper on top and bottom. top copper layer has a dedicated 125 sqmm copper area.
ncp720 www. onsemi.com 3 electrical characteristics over operating temperature range (t j = ?40 c to +125 c), v bias = (v out + 1.4 v) or 2.5 v, whichever is greater; v in v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, unless otherwise noted. typical values are at t j = +25 c. parameter test conditions symbol min typ max unit operating input voltage range v in v out + v do _ in 5.5 v operating bias voltage range v bias (v out + 1.4) 2.4 5.5 v output voltage range (note 4) 0.8 2.1 v output voltage accuracy nominal t j = +25 c v out 0.5 % over v bias , v in , i out , t j = ?40 c to +125 c v out + 1.4 v v bias 5.5 v, v out + 0.5 v v in 4.5 v, 0ma i out 350 ma v out -2 +2 % v in line regulation v in = (v out + 0.5 v) to 4.5 v, i out = 1ma v out / v in 5.0 v/v v bias line regulation v bias = (v out + 1.4 v) or 2.5 v (which- ever is greater) to 5.5 v, i out = 1 ma v out / v bias 16 v/v load regulation 0 ma i out 350 ma (no load to full load) v out / i out ?1.0 v/ma v in dropout voltage (note 5) v in = v out(nom) ? 0.1 v, (v bias ? v out(nom) ) = 1.4 v, i out = 350 ma v do _ in 110 200 mv v bias dropout voltage (note 6) v in = v out(nom) + 0.3 v, i out = 350 ma v do _ bias 1.15 1.4 v output current limit v out = 0.9 x v out(nom) i cl 420 525 800 ma bias pin current i out = 0 ma to 350 ma i bias 80 110 a shutdown current (i gnd ) v en 0.4 v, t j = -40 c to +85 c i shdn 0.5 2.0 a v in power-supply rejection rati o v in ? v out 0.5 v, v bias = v out + 1.4 v, i out = 350 ma f = 10 hz psrr (v in ) 52 db f = 100 hz 56 f = 1 khz 65 f = 10 khz 46 f = 100 khz 37 f = 1 mhz 25 v bias power-supply rejection ratio v in ? v out 0.5 v, v bias = v out + 1.4 v, i out = 350 ma f = 10 hz psrr (v bias ) 65 db f = 100 hz 65 f = 1 khz 70 f = 10 khz 50 f = 100 khz 35 f = 1 mhz 24 output noise voltage bw = 10 hz to 100 khz v n 40 v rms inrush current on v in i vin_inrush 100 + i load ma startup time v out = 95% v out(nom) , i out = 350 ma, c out = 2.2 f t str 140 s enable pin high (enabled) v en(hi) 1.1 v enable pin low (disabled) v en(lo) 0 0.4 v enable pin current v en = 5.5 v i en 0.3 1 a undervoltage lock-out v bias rising uvlo 1.6 v hysteresis v bias falling 0.2 v thermal shutdown temperature shutdown, temperature increasing t sd +160 c reset, temperature decreasing +140 c operating junction temperature t j ?40 +125 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. v out nominal value is factory programmable. 5. measured for devices with v out(nom) 1.2v. 6. v bias ? v out with v out = v out(nom) ? 0.1v.
ncp720 www. onsemi.com 4 applications information in en fb lx gnd processor i/o bias in out gnd ncp720 load vbat . to other circuits i/o en figure 3. typical application: low?voltage post?regulator with on/off functionality dc/dc
ncp720 www. onsemi.com 5 typical characteristics v out(nominal) = 1.5 v, v bias = (v out + 1.4 v) or 2.5 v, whichever is greater, v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, t j = 25 c unless otherwise noted. figure 4. v in dropout voltage vs. output current figure 5. v bias dropout voltage vs. temperature figure 6. output voltage vs. temperature figure 7. bias pin current vs. v bias input voltage figure 8. bias pin current vs. output current figure 9. bias pin current vs. temperature
ncp720 www. onsemi.com 6 typical characteristics v out(nominal) = 1.5 v, v bias = (v out + 1.4 v) or 2.5 v, whichever is greater, v in = v out + 0.5 v, i out = 1 ma, v en = 1.1 v, c out = 2.2 f, t j = 25 c unless otherwise noted. figure 10. shutdown current vs. v bias input voltage figure 11. current limit vs. v bias input voltage figure 12. current limit vs. v in input voltage figure 13. v in power supply ripple rejection vs. frequency figure 14. v bias power supply ripple rejection vs. frequency figure 15. load transient response i out 100ma/div v out 50mv/div t rise = 1 s 300 ma 0 ma
ncp720 www. onsemi.com 7 applications information the ncp720 dual?rail very low dropout voltage regulator is using nmos pass transistor for output voltage regulation from v in voltage. all the low current internal controll circuitry is powered from the v bias voltage. the use of an nmos pass transistor offers several advantages in applications. unlike a pmos topology devices, the output capacitor has reduced impact on loop stability. v in to v out operating voltage difference can be very low compared with standard pmos regulators in very low v in applications. the ncp720 offers built?in soft?start with monotonic v out rise. the controlled voltage rising limits the inrush current. the enable (en) input is equipped with internal hysteresis. ncp720 is a fixed voltage linear regulator. dropout voltage because of two power supply inputs v in and v bias and one v out regulator output, there are two dropout voltages specified. the first, the v in dropout voltage is the voltage difference (v in ? v out ) at which the regulator output no longer maintains regulation against further reductions in input voltage. v bias is high enough, specific value is published in the electrical characteristics table. the second, v bias dropout voltage is the voltage difference (v bias ? v out ) at which the regulator output no longer maintains regulation against further reductions in v bias voltage. v in is high enough. input and output capacitors the device is designed to be stable for ceramic output capacitors with effective capacitance in the range from 2.2 f to 10 f. the device is also stable with multiple capacitors in parallel, having the total effective capacitance in the specified range. in applications where no low input supplies impedance available (pcb inductance in v in and/or v bias inputs as example), the recommended c in = 1 f and c bias = 0.1 f or greater. ceramic capacitors are recommended . for the best performance all the capacitors should be connected to the ncp720 respective pins directly in the device pcb copper layer, not through vias having not negligible impedance. when using small ceramic capacitor, their capacitance is not constant but varies with applied dc biasing voltage, temperature and tolerance. the ef fective capacitance can be much lower than their nominal capacitance value, most importantly in negative temperatures and higher ldo output voltages. that is why the recommended output capacitor capacitance value is specified as effective value in the specific application conditions. enable operation the enable pin will turn the regulator on or off. the threshold limits are covered in the electrical characteristics table in this data sheet. if the enable function is not to be used then the pin should be connected to v in or v bias . when enabled, the device consumes roughly 20 a from vin supply per 1 v nominal output voltage. that is why using the enable / disable function in power saving applications is recommended. current limitation the internal current limitation circuitry allows the device to supply the full nominal current and surges but protects the device against current overload or short. thermal protection internal thermal shutdown (tsd) circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when tsd activated , the regulator output turns off. when cooling down under the low temperature threshold, device output is activated again. this tsd feature is provided to prevent failures from accidental overheating.
ncp720 www. onsemi.com 8 ordering information device nominal output voltage marking package shipping ? ncp720bmt100tbg 1.00 v jc wdfn6 (pb?free) 3000 / tape & reel ncp720bmt105tbg 1.05 v jd ncp720bmt1110tbg 1.10 v je ncp720bmt115tbg 1.15 v jf ncp720bmt120tbg 1.20 v jg ncp720bmt125tbg 1.25 v jh ncp720bmt130tbg 1.30 v jj ncp720bmt135tbg 1.35 v jk ncp720bmt140tbg 1.40 v jl ncp720bmt145tbg 1.45 v jm ncp720bmt150tbg 1.50 v ja ncp720bmt160tbg 1.60 v jp ncp720bmt170tbg 1.70 v jq NCP720BMT180TBG 1.80 v jr ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging spe- cifications brochure, brd8011/d. to order other package and voltage variants, please contact your on sales representative
ncp720 www. onsemi.com 9 package dimensions wdfn6 2x2, 0.65p case 511br issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 2.00 bsc d2 1.50 1.70 0.90 1.10 e 2.00 bsc e2 e 0.65 bsc 0.20 0.40 l pin one reference 0.05 c 0.05 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 4 0.05 c mounting footprint bottom view recommended dimensions: millimeters l1 detail a l alternate constructions l ??? --- 0.15 l1 6x 0.45 2.30 1.12 1.72 0.65 pitch 6x 0.40 1 package outline 6x m m on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp720/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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